The present invention relates to debugging support circuitry. More specifically, the present invention relates to circuitry that adds additional debugging functionality to a test access port (TAP) controller circuit.
As printed circuit boards (PCBs) have become more complex, the need for thorough testing becomes increasingly important. Advances in surface-mount packaging and PCB manufacturing have resulting in smaller boards, making traditional testing (e.g., external test probes and “bed-of-nails” test fixtures coupled to numerous pins on the PCB) harder to implement. As a result, cost savings from PCB space reductions are sometimes offset by cost increases in traditional testing methods.
In the 1980's, the Joint Test Action Group (JTAG) developed a specification for boundary-scan testing that was later standardized as the IEEE std. 1149.0-1990 specification. This boundary-scan testing (BST) architecture offers the capability to efficiently test components on PCBs with tight lead spacing. This BST architecture can test pin connections without using physical test probes and capture functional data while a device is operating normally.
BST circuitry typically includes a TAP controller, an instruction register, and data registers. Each data register is configured in hardware to perform one or more functions such as testing and debugging on stored and inputted data. An example of a data register is a boundary scan register which includes boundary-scan cells in a device that can force signals onto pins, or capture data from pin or core logic signals. Test data forced onto pins is serially shifted into the boundary-scan cells. Data captured from pins or core logic signals is serially shifted out and externally compared to expected results. Further details information regarding BST architecture is discussed in “IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices,” Application Note 39, August 1999, pp. 1–29.
The functionality of pre-existing BST circuitry is limited by the hardware configuration of the data registers. To add further testing and debugging functionality to the BST circuitry, additional data registers must be designed into the BST circuitry in advance. The functionality of BST circuitry is therefore limited by the hardware design of the device.
It would therefore be desirable to provide test scan circuitry that augments the functionality of a pre-existing JTAG BST circuit device.
It would also be desirable to provide additional test scan circuitry that can be configured to be compatible with any BST circuit device.